Written by Lucas Teske
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Big Gate Boy

An open FPGA experiment that rebuilds the Game Boy in programmable logic and aims it at a gloriously oversized six-panel display.

Open hardware · FPGA · Verilog

Game Boy, rebuilt gate by gate.

Big Gate Boy explores a Game Boy-compatible CPU in Verilog for a Lattice ECP5, with six LED panels as the oversized display target. The source, tests, live sessions, and panel reverse engineering are collected here.

Browse the source Watch the build
Game Boy graphics running across a large LED panel
  1. CPU core and opcode map
  2. Assembly tests
  3. Panel reverse engineering
  4. Six-panel display target

Explore the build

Start with the layer that interests you: processor logic, unusual display hardware, recorded sessions, or source code.

Processor reference

CPU core and instruction map

Read the opcode conventions, register groups, ALU operations, and instruction map used while implementing the core.

Open the microcode reference
Display hardware

LYD6168 panel research

Follow the investigation that identified the undocumented LYD6168 panels as MBI5153-compatible hardware.

Read the panel investigation
Build in public

Development sessions

Watch the project take shape in the recorded livestream sessions, from CPU work to hardware experiments.

Open the YouTube playlist
Open source

Verilog, tests, and tooling

Browse the CPU modules, ALU and register-bank test benches, assembly test programs, constraints, and build tooling.

View the repository

Display research notes

Practical references produced while turning six unfamiliar LED panels into usable project hardware.